RTL integration Engineer
Core
Perform IP integration, test/debug mode verification, and RTL design creation at the SoC level.
Role type
Senior RTL integration engineer
Builds
SoC-level integrated IP blocks
Domain
Semiconductor hardware design / RTL verification
Required skills
SystemVerilog, UVM, RTL design, synthesis, timing analysis, gate-level simulation (GLS), Clock Domain Crossing (CDC) analysis, zero-delay and SDF simulation debugging
Preferred skills
NCSim, VCS, independent work, rapid tool adaptation
Technologies
SystemVerilog, UVM, NCSim, VCS
Responsibilities
Create RTL designs, perform linting, execute CDC and RDC analysis, handle synthesis, support palladium modeling and STA, debug RTL and gate-level failures
Seniority
Senior, hands-on IC
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