ASIC Physical Design
1,645 open positions
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Principal Engineer- CPU Circuit Design IntelIndia, Bangalore 22d Lead the development of advanced digital circuits for custom blocks including SRAM, register files, memory compilers, custom data paths, and caches.
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Principal Physical Design Engineer - MCU NxpCatania $61k–$61k22d Lead physical design and implementation of complex, high-performance semiconductor integrated circuits for micro-controllers (MCUs) and edge processing solutions.
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Design Engineer↗ ArmKA, IN 22d Develop transistor-level physical layouts for Arm custom standard cells in sub-3nm process nodes to deliver high-performance, area-optimized logic libraries for next-generation SoCs and custom digital IPs.
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FPGA Design Engineer (EAD -CPT, EAD - OPT) permitted↗ Silicon InterfacesMountain View, CA, US $62k–$62k22d Design, develop, and optimize FPGA architectures for communications and control systems, integrating them with embedded systems and conducting hardware verification.
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ASIC Design Engineering Manager, Lund AxisSweden - Lund 22d Lead the ASIC Design team to develop next-generation ARTPEC SoC/ASIC designs for real-time image processing, video compression, and computer vision in security cameras.
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Physical Design Engineer/STA AlteraRegus, Madhapur 22d Performs physical design implementation of custom IP and SoC designs from RTL to GDS, conducting verification and signoff to create manufacturing-ready design databases.
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Staff Silicon Physical Design Engineer - Bengaluru GraphcoreBengaluru 24d Designing high-performance, power-efficient AI superchips at leading-edge process nodes using state-of-the-art EDA tools and in-house flows.
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FPGA Design Engineer - 964 QuantinuumUS Broomfield, CO 24d Lead FPGA design for the digital control system of quantum computers, coordinating electronics and processing signals.
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FPGA Design Engineer↗ Aten Canada Technologies Inc.Richmond, BC, CA $60k–$60k24d Develop and verify high-speed FPGA systems and implement data/signal processing algorithms for world-leading KVM switches.
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?SoC-FPGA Entwickler (m/w/d) Backnang, BADEN_WUERTTEMBERG 24d Design, verification, and deployment of complex FPGA/SoC solutions for high-tech industrial manufacturing systems.
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FPGA Designer↗ Lumentum OperationsOttawa, ON, CA $93k–$93k24d Design control and datapath logic for next-generation optical cloud and networking technology using FPGAs.
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Principal Design Engineer MicrosoftUnited States, California, Mountain View 25d Leading high-performance, high-bandwidth digital design for IP microarchitecture, RTL, synthesis, and SoC integration.
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Principal Electrical Design Engineer AsteralabsSan Jose 25d Define and drive architecture, design, and technical strategy for advanced board-level hardware across next-generation networking and high-performance connectivity platforms.
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Semiconductor Design Engineer MicronSan Jose, CA $174k–$174k25d Design and validate on-chip controllers and mixed-signal circuitry for NAND Flash chips, including architecture development, system integration, and full-chip validation.
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Researchers (Secure FPGA Design and Verification)↗ Tum Create LimitedClementi, S00, SG 25d Developing an open and verifiable Quantum safe RISC-V processor platform for post-quantum security research.
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Physical Design Engineer Intern, MS - Summer 2027 MarvellSanta Clara, CA, US $71k–$141k25d Intern role focused on physical design of ASIC and processor designs, performing synthesis, floor planning, place and route, and timing closure for next-gen data center chips.
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Digital Design Engineer SilabsOslo $479k–$479k25d Develop digital architectures, IP, processors, compute engines, and peripherals for Silicon Labs IoT mixed-signal SoCs.
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Physical Design Engineer↗ Marvell TechnologyCórdoba, X, AR 25d Physical design and methodology for next-generation high-performance processor chips in leading-edge CMOS process technology.
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SRAM Physical Design Engineer↗ AMDBoxborough, MA, US 25d Design and optimize high-performance SRAM and memory structures for next-generation CPU cores.
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?Senior Softwareingenieur FPGA / VHDL (m/w/d) Ulm, Donau, BADEN_WUERTTEMBERG 25d Develop and implement FPGA and VHDL-based solutions and FPGA firmware for embedded systems.
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Sr HW Design Engineer FfiveSpokane Valley, US $161k–$161k25d Lead system-level hardware design for high-performance electronic systems, driving development from concept through production release.
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Senior ASIC Engineer, Switch SoC NVIDIAIndia, Bengaluru 25d Design and integrate next-generation Switch Silicon chips, defining system-level methodologies and driving cross-functional teams to deliver high-throughput, low-latency communication devices.
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FPGA Designer LumentumCanada - Ottawa (Bill Leathem) $93k–$93k25d Design control and datapath logic for advanced photonic modules powering AI, cloud computing, and telecom networks.
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Sr. Director, SoC Architecture AmbiqmicroincAustin HQ 26d Define system architecture for next-generation ultra-low-power AI SoCs powering wearables, IoT, and battery-constrained edge devices.
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Senior Principal Engineer, Physical Design Methodology & RTL-to-GDS Architecture SiFiveBengaluru, Karnataka, India 26d Chief visionary and architect of the physical implementation backbone for next-generation, high-frequency CPU cores, pioneering AI-native automated methodologies for sub-3nm nodes.
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Digital Design Engineer Lead - Custom Silicon Management↗ AppleAustin, TX, US $176k–$176k26d Lead technical engagements between Apple and silicon suppliers to define, develop, and productize custom silicon for mobile products including iPhone, iPad, and AppleTV.
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Leader, Hardware Engineering - 10+ years of proven experience as Product/Design Engineer with expertise in electronic product design and architecture. CiscoBangalore, India 26d Lead a product engineering team delivering high-performance routers and switches (Cisco 8000 series) using Silicon One ASIC architecture for AI and 5G networks.
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ASIC Development Engineer↗ Microchip TechnologyBurnaby, BC, CA $76k–$76k26d Design, verification, emulation, and validation of digital integrated circuits (SoCs) for storage and memory controllers.
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Power Engineering Architect CerebrasSunnyvale, CA $230k–$230k26d Lead power delivery architecture and strategy for high-performance compute, AI/ML accelerators, and advanced ASIC platforms.
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CPU Physical Design Timing Engineer↗ QualcommSanta Clara, CA, US $199k–$199k26d Define, develop, and drive CPU timing closure for Oryon CPU cores, working with microarchitecture and RTL design teams to meet aggressive power, area, and performance goals.
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Senior Physical Design Engineer - P&R↗ Bta Design ServicesRemote 26d Senior Physical Design Engineer owning backend implementation from netlist to GDSII for advanced silicon platforms targeting next-gen AI infrastructure.
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?FPGA und Embedded Software Ingenieur (m/w/d) Remote 26d Design and verification of FPGA modules for Xilinx SoCs, development of C++ drivers, and embedded signal processing software in C++ (RTOS).
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System IP RTL Design Lead TenstorrentBengaluru 27d Lead the definition, selection, and integration of complex datacenter-class System IP and SoC architectures for next-generation semiconductor products.
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