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Software Engineering
› Hardware Verification
Hardware Verification
783 open positions
Sr. Principal Software Engineer, Physical Verification
Cadence
SAN JOSE
$161k–$299k
12d
Design, develop, and implement robust software for physical verification of advanced semiconductor devices at leading-edge nodes.
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Internship Position (Digital Signoff Group)
Cadence
CORK 01
12d
Software Engineering Intern contributing to real product features for a parasitic analysis and debugging platform used by semiconductor engineers.
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Semiconductor Software Engineer
↗
BV Teck
Remote
$100k–$100k
12d
Design and build software tooling, firmware, and infrastructure to accelerate semiconductor design, verification, and post-silicon validation workflows.
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SRAM Software Engineer Intern, BS - Summer 2027
Marvell
Burlington, VT
$62k–$123k
12d
Design, verify, and characterize high-performance SRAM memory for cutting-edge semiconductor technologies and AI infrastructure.
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Lead Software Engineer
Cadence
Burlington, MA
$102k–$102k
12d
Developing the world's fastest emulator compiler for Cadence's Palladium Platform, focusing on large-scale compile problems like logic optimization, distributed databases, and precompiler technologies.
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Founding Engineer
Clera
USA
$120k–$120k
12d
Build and ship AI-assisted PCB design tools and EDA automation features, integrating manufacturing pipelines to own the end-to-end hardware-to-production workflow.
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MEMS Layout
Bosch-Group
Milano, Lombardia, it
$40k–$40k
13d
Develop holistic chip designs and layouts for complex micromechanical sensors, generate mask data, and optimize software for simulation and verification.
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Configuration and Change Manager (f/m/d)
Renesas-Electronics
Graz, at
$0k–$0k
13d
Manage configuration and change control for semiconductor development programs, ensuring traceability from design to post-silicon validation.
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Stage Ingénieur : Développement d’un outil d’analyse de performance pour simulations hardware (H/F)
Nxp
Caen
13d
Develop an internal tool to extract and measure performance indicators from hardware simulations of digital components.
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Stage ingénieur : Analyse de la consommation et optimisation des tests pour les System-on-Chip (SoC) de nouvelle génération (H/F)
Nxp
Sophia-Antipolis (Valbonne)
13d
Analyzing power consumption and optimizing test quality for next-generation System-on-Chip (SoC) designs using AI and automation.
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Stage Ingénieur : Application de l'Intelligence Artificielle à l'intégration de blocs RTL (ASIC/FPGA) (H/F)
Nxp
Sophia-Antipolis (Valbonne)
13d
Develop an AI-based solution to automate and improve the reliability of RTL IP integration within ASIC and FPGA projects.
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Quartus Compiler Software - Intern
Altera
Toronto, Ontario, Canada
$95k–$95k
13d
Design, code, and test software for the Quartus FPGA compiler, specifically improving synthesis, place and route, and timing analysis engines.
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Field Applications Engineer (FAE)
Altera
Remote
$135k–$135k
13d
Drive FPGA adoption and provide technical support to customer engineering teams for Altera programmable logic solutions.
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Senior Thermal-Fluids Engineer – Advanced Cooling
↗
Diamond Foundry
Zaragoza, AR, ES
13d
Lead the design, prototyping, and experimental validation of advanced liquid cooling architectures for high-performance semiconductor thermal management using single-crystal diamond.
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Stage ingénieur : Développement d’outils d’Intelligence Artificielle pour l’automatisation et la capitalisation des connaissances EMC/ESD (H/F)
Nxp
Toulouse
13d
Develop AI workflows and intelligent assistants to automate engineering activities and structure historical technical knowledge for EMC/ESD robustness in integrated circuit design.
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Electrical Engineer - NPI
↗
ASML
Wilton, CT, US
13d
Develop complex electrical hardware, interconnects, controls, and integration solutions for ASML's High Productivity Platform (HPP) lithography systems.
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Lead Product Engineer
Cadence
BANGALORE
13d
Lead Product Engineer responsible for Synthesis flows including Logic Equivalence Checking (LEC) and Clock Latency Planning (CLP) to address design issues.
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Hardware Engineer I (Intern) - United States
Cisco
San Jose, California, US
$44k–$44k
13d
Intern role supporting hardware engineering across diverse product categories including ASIC design, system/board design, circuit layout, validation, signal integrity, and power design.
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Senior Product Engineer (DFT)
↗
AMD
Tampines, S00, SG
14d
Drive next-generation DFT solutions, engineering productivity, and data-driven decision making across AMD semiconductor products.
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Senior Burn-In System Product Developer
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AMD
Bedok, S00, SG
14d
Lead architecture, development, and deployment of next-generation burn-in solutions for advanced semiconductor products (CPUs, GPUs, AI accelerators, chiplets) to ensure product quality, reliability, and manufacturing excellence.
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Senior SW Backend Engineer
Amat
Rehovot,ISR
14d
Design and develop backend software in Java to control and manage next-generation semiconductor metrology and inspection systems, orchestrating complex scan-domain system flows.
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Virtuoso Custom CAD Engineer
Apple
Sunnyvale, United States of America
14d
Provide full support for Cadence custom flows, tool development, installation, and maintenance for digital, analog, and mixed-signal designs.
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FPGA Development Tools Engineer
Altera
Toronto, Ontario, Canada
$110k–$110k
14d
Researches, designs, develops, and optimizes software tools (compilers, flows, assemblers, models, runtimes, firmwares) and software abstractions for Field Programmable Gate Arrays (FPGA) acceleration.
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Virtuoso Custom CAD Engineer
Apple
San Diego, United States of America
14d
Provide full support for Cadence custom flows, tool development, installation, and maintenance for digital, analog, and mixed-signal designs.
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Staff Engineer - NVE PE
Micron
Penang, Malaysia - Grande
14d
Staff Engineer leading infrastructure, automation, and AI-enabled workflows for NAND flash and non-volatile storage product development and qualification.
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Senior Data Engineer (f/m/div)
↗
Infineon Technologies
Villach, K, AT
14d
Design and implement data processing pipelines to ingest, transform, and serve large volumes of data for post-silicon verification of semiconductors.
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Product Engineering Architect
Cadence
AUSTIN
14d
Manage and execute digital implementation, signoff, and verification flows for customers, leading new process technology platform enablement and PPA realization.
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MEMS Layout
Bosch-Group
Milano, Lombardia, it
$40k–$40k
15d
Develop holistic chip designs and layouts for complex micromechanical sensors, generate mask data, and optimize software for layout verification.
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Software Development Engineer
Siemens
USA
15d
Develop and optimize compiler solutions and tools using C/C++ on UNIX/Linux platforms for EDA applications.
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Field Applications Engineer
Siemens-Eda
Shanghai, CHN, China
15d
Pre-sales and post-sales technical support for Electronic Design Automation (EDA) software, driving customer adoption and sales campaigns.
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Staff Design Automation Engineer
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Skyworks Solutions
KA, IN
15d
Build Python-based web platforms and automation tools to modernize RF/AMS module packaging and back-end IC wafer flows, replacing legacy spreadsheet/VBA processes with database-driven systems.
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Senior / Staff Embedded Applications Engineer
Altera
Penang 15, Penang, Malaysia
15d
Provide technical support, training, and design validation for Altera FPGA features (Embedded IP, Processor solutions, Flash) to enable customer design wins.
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Lead Software Engineer - Low Power Verification
Cadence
SAN JOSE
$115k–$115k
15d
Lead Software Engineer improving performance and usability of UPF debug features for multi-billion-gate low-power designs on Palladium and Protium emulation platforms.
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System Technology Research Engineer - (PhD Intern)
Intel
US, Oregon, Hillsboro
$142k–$142k
15d
Develop System Technology Co-optimisation (STCO) methodologies and evaluate 3D/2.5D dis-aggregation schemes using solder microbumps or hybrid bonding for memory and logic stacking.
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Physical Design Sign-off Engineer
Apple
Austin, United States of America
15d
Develop full-stack web applications, dashboards, and data visualization tools for the Signoff infrastructure used by Apple SOC design groups to validate chip designs against manufacturing, timing, and power criteria.
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Software Engineer II
Cadence
SHANGHAI, CN
15d
Develop new features, maintain existing product functionalities, and optimize performance for EDA applications.
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Node Development Product Engineer
Micron
Taichung - Fab 16, Taiwan
15d
Bringing up new DRAM technology nodes from design start through qualification and production ramp while co-optimizing product and process.
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Silicon Design - Flows and Methodology Intern
↗
Intel Corporation
Guadalajara, JAL, MX
15d
Develop and document silicon design tools, flows, and methodologies to drive innovation in memory-related IP design.
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Software Development Engineer
↗
Siemens
UP, IN
18d
Develop and optimize compiler solutions and tools for Electronic Design Automation (EDA) applications to enable faster chip, board, and system design.
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Systems Engineering Intern
Texas Instruments
Dallas, TX, United States
18d
Develop advanced analog and digital chips and system products from concept to mass production, including high-speed IC design cycles and system design activities.
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VLSI Software Engineer
↗
Qualcomm
Tijuana, BCN, MX
18d
Develop internal CAD tools and methodologies for top-level chip floorplanning, RTL module placement, and datapath pipeline routing to optimize timing and area for Snapdragon chips.
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Lead Software Engineer
Cadence
SAN JOSE
$115k–$213k
18d
Designing, developing, and debugging a multi-threaded, distributed physical synthesis core engine for the Innovus Implementation System.
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Summer Program Intern
Marvell
Cordoba, Argentina
18d
10-week immersive summer program for engineering students to rotate through technical tracks in coherent optical technology.
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Summer Program Intern
↗
Marvell Technology
Córdoba, X, AR
18d
10-week immersive summer program for engineering students to rotate through technical tracks in coherent optical technology.
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Research Engineer, AI for Chip Design
OpenAI
San Francisco
18d
Build RL environments and evaluations to help AI models solve chip-design problems like RTL generation, design verification, and physical design optimization.
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Layout Automation Developer Intern - 993
Quantinuum
US Brooklyn Park, MN
18d
Develop Python and SKILL based automation tools to accelerate the physical layout of ion traps and related chips.
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Software Engineer - C++ / Digital Logic
Siemens-Eda
Waltham, MA, United States
$105k–$105k
19d
Develop and improve the compiler software for hardware emulators used in functional verification of System-on-Chip circuit designs.
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Lead Software Engineer
Cadence
ZHUBEI 01
19d
Develop the world's fastest emulator compiler for the Cadence Palladium Platform, focusing on large-scale compile problems like logic optimization, logic modeling, and data structures for emulation.
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AI Design Automation Engineer
↗
AMD
San Jose, CA, US
19d
Build AI-powered engineering platforms and backend data pipelines to help semiconductor design teams access, query, and leverage complex engineering data using natural language and knowledge graphs.
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Senior PDK Support Engineer (Physical Verification)
Intel
US, California, Santa Clara
$174k–$330k
19d
Support Physical Verification (DRC/LVS/ERC/Density/LU) for Intel leading edge PDKs, performing PV runs, identifying violations, and implementing solutions.
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