ASIC Physical Design
1,644 open positions
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ASIC Design and Integration Engineer – Silicon Security AppleCupertino, United States of America 1mo Designing and integrating secure hardware subsystems (cryptographic engines, side-channel monitors) to protect Apple SoCs from attacks.
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Sr. PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning
AmazonAustin, Texas, United States
$159k–$215k1mo
Design and optimize hardware methodologies for custom ML accelerator chips (AWS Inferentia, Trainium) in advanced nodes to enable cloud-scale machine learning.
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Design Engineer - Timing Methodology BroadcomUSA-California-San Jose-1320 Ridder Park Drive $144k–$144k1mo Develop and deploy advanced timing sign-off methodologies, modeling, and solutions for SOC and 3D/2.5D IC designs to ensure high yield and optimized margins.
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Hardware Engineer CiscoHsinchu, Taiwan 1mo Design next-generation Hyperscaler Switch hardware based on Silicon One and merchant ASIC, including CPU subsystems, system specifications, and board-level bring-up.
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Senior SoC Design Engineer NVIDIAIndia, Bengaluru 1mo Design next-generation System on Chips (SoCs) and subsystems, ensuring first-time-right designs through collaboration with architecture, verification, and IP teams.
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Senior Hardware Design Engineer SambanovasystemsAustin, TX $120k–$120k1mo Design component units of the Reconfigurable Dataflow Unit (RDU) ASICs for AI workload acceleration systems.
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HPC Quality Leader for Automotive SoC (R‑Car) Design Team Renesas-ElectronicsKodaira, jp 1mo Lead design quality and risk management across the entire automotive SoC (R-Car) design team, ensuring stable development of integrated IP including CPU, interfaces, memory, AI, and video.
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Staff Engineer AI/ML GlobalFoundriesSanta Clara, US $143k–$143k1mo Lead RTL development and micro-architecture design for AI-enabled RISC-V CPU cores, including vector extensions and matrix engines.
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?FPGA-Entwickler VHDL (m/w/d) Bremen, BREMEN 1mo Designing and implementing digital circuits on FPGA platforms, verifying designs, and integrating modules into hardware/software systems.
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Senior Physical Design Engineer MicrosoftUnited States, North Carolina, Raleigh 1mo End-to-end execution of physical design for large System-on-Chip (SOC) blocks, covering synthesis, place-and-route, and all signoff stages.
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Staff Physical Design Engineer-DPG-LPDDR MicronHyderabad - Phoenix Aquila, India 1mo Lead end-to-end RTL-to-GDSII implementation for complex SoCs across advanced technology nodes, driving floor planning, power planning, CTS, place & route, and physical signoff.
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Senior Principal Engineer, Physical Design Engineering AnalogdevicesIndia, Bangalore, RMZ 1mo Lead SoC execution from spec to silicon, driving technical strategy and architecture for complex digital systems.
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ASIC Design Engineer↗ GmvTres Cantos, Community of Madrid, Spain 1mo Design and migrate GNSS receiver architectures from FPGA/MPSoC to ASIC solutions, focusing on RTL development, architecture optimization, and ASIC flow implementation.
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Digital IC Design Engineer (New Grad) MonolithicpowerHong Kong - China 1mo Design and implement digital and mixed-signal chips (SoC) for power management, automotive electronics, LED lighting, networking, and charging.
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Staff CPU Architect↗ Openchip & Software TechnologiesLimerick, County Limerick, Ireland 1mo Leading architectural and micro-architectural specification for next-generation OOO superscalar CPU cores in SoC designs, focusing on performance and power/area efficiency.
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ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs
AmazonCupertino, California, United States
$157k–$157k1mo
Design and optimize high-performance, power-efficient custom SoCs (System on Chip) for AWS Machine Learning inference servers, specifically the Inferentia architecture.
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SoC Compute/Memory Subsystem Architect IntelIreland, Leixlip $75k–$75k1mo Define and drive end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and high-performance memory subsystems for next-generation IPU/DPU platforms.
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Physical Design Engineer, AI Accelerator IP TenstorrentAustin $100k–$100k1mo End-to-end physical implementation of RISC-V CPU and AI accelerator IP blocks for external licensees, ensuring PPA targets and timing closure.
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SoC Design & Synthesis Engineer↗ QualcommTijuana, Baja California, Mexico 1mo Synthesizing large-scale SoC RTL designs into high-quality gate-level netlists ready for Place & Route, optimizing PPA, and supporting functional ECOs for Snapdragon products.
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Template Job AsteralabsVancouver $133k–$133k1mo Design and implement complex digital blocks for rack-scale AI connectivity silicon, ensuring silicon-ready quality from microarchitecture to tapeout.
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Director, ASIC Design & Front-End Implementation HpeRoseville, California, United States of America 1mo Lead the ASIC Design and Front-End Implementation organization to deliver next-generation networking ASICs powering HPE Networking products.
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Physical Design Engineer AlteraSan Jose, California, United States $119k–$119k1mo Implement custom IP and SoC designs from RTL through GDSII, focusing on timing closure, power optimization, and physical verification for next-generation FPGA technologies.
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Silicon Architect OuraSan Francisco, CA, United States $180k–$180k1mo Define custom silicon architectures and roadmaps for next-generation wearable health products, translating system needs into silicon specifications.
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Senior/Staff Engineer - Logical Design Axelera-AIRemote 1mo Architect and implement advanced micro-architectures for silicon components, ensuring optimal performance, power, and area (PPA) metrics for in-house AI products.
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Intern Digital IC Design ON SemiconductorMarin-Epagnier, Neuchatel, Switzerland 1mo Simulate, evaluate, and build low-power digital subsystems for microcontrollers and SoCs, verifying designs on FPGA.
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Lead Engineer – IC Design (STA Lead ) SilabsHyderabad 1mo Lead Physical Design Engineer responsible for end-to-end backend implementation flow, timing sign-off, and PPA optimization for high-performance SoCs and ASICs.
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Digital IC Design/Verification Engineer↗ Marvell TechnologyCordoba, Córdoba, Argentina 1mo Implementing digital logic blocks for high-speed coherent transceivers in PCIe systems, including RTL design, verification, and automated test case development.
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FPGA Developer (f/m/x) ZeissgroupOberkochen 1mo Design and implement FPGA-based digital logic, develop custom IP cores, and optimize designs for timing, power, and performance.
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