ASIC Physical Design
1,648 open positions
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Senior Staff / Principal SOC Floorplan Lead Enchargeai36India 1mo Own the physical foundation of next-generation AI and Data Center SoCs, bridging architecture, logic design, and physical design to achieve best-in-class Power, Performance, and Area (PPA).
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Hardware Engineer (FPGA/ASIC) JanestreetLondon 1mo Intern role focused on using programming language technology (OCaml/Hardcaml) to improve the design, testing, and validation of hardware designs.
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Senior Chip Design Engineer NVIDIAIsrael, Tel Aviv 1mo Design and implement next-generation Switch Silicon chips, focusing on high-speed communication devices with high throughput and low latency.
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Chip Design Engineer, Nitro Chip Design Team
AmazonTel Aviv-Yafo, Tel Aviv, Israel
1mo
Design and develop custom silicon micro-architecture and RTL for the Nitro System on Chip (SoC) that underpins AWS cloud instances.
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Digital Design Engineer – AI Accelerators StmicroelectronicsGreater Noida, India 1mo Design and implement high-throughput compute datapaths and microarchitectures for AI accelerator chips, integrating compute blocks with memory interfaces.
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Camera Design Engineer↗ QualcommVancouver, British Columbia, Canada $84k–$84k1mo Design world-class image and video processing blocks and core-level IP for multimedia camera systems.
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AI-Driven ASIC Physical Design Principal Engineer CiscoSan Jose, California, US $251k–$251k1mo Principal AI engineer building agentic physical design workflows and LLM-based copilots to automate ASIC physical design tasks like placement, routing, and timing analysis.
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Senior Principal ASIC Design Engineer AsteralabsGermany 1mo Senior technical leader driving ASIC design for next-generation Ethernet and Scale-Up (ESUN) connectivity products for rack-scale AI infrastructure.
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Principal Subsystem Engineer (Design or DV) MicrosoftUnited States, California, Mountain View 2mo Lead the design or design verification of complex, high-performance custom IP and System on Chip (SoC) subsystems, focusing on AI/ML SoCs and delivering silicon from concept through bring-up.
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Hardware Engineer Western-DigitalSan Jose, CA, us 2mo Design custom silicon, electronic hardware, embedded firmware, and mechanical systems for next-generation hard disk drives and data storage products.
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SRAM Circuit Design Engineer AppleBeaverton, United States of America 2mo Design and implement custom digital SRAM circuits for Apple's high-performance silicon products (M1, A14 Bionic, etc.), optimizing for power, timing, area, and yield.
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Principal Digital Design Engineer AnalogdevicesGermany, Munich, Seidlstr 2mo Lead digital RTL development and architecture for complex digital controllers in power management ICs (PMICs) and mixed-signal ICs using FinFast™ technology.
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RTL integration Engineer BroadcomUSA-CA San Jose Innovation Drive $144k–$144k2mo Perform IP integration, test/debug mode verification, and RTL design creation at the SoC level.
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Principal DFT Engineer (Silicon Engineering) SpaceXAustin - 800 2mo Lead implementation and optimization of DFT architectures for next-generation ASICs deployed in space and ground infrastructures to enable global connectivity.
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Staff Digital Design Engineer NxpBangalore 2mo Lead architecture, implementation, and integration of digital subsystems for Automotive Ethernet PHY products (10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1, and multi‑gig automotive SerDes technologies), driving digital micro-architecture, state machines, PCS…
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2027 Internship - FPGA Engineer Virtu FinancialDublin, Ireland 2mo Intern role focused on FPGA and ASIC design for ultra-low latency trading systems, working from architecture through RTL implementation, simulation, verification, and hardware bring-up.
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Senior Principal Engineer – Hardware Chip Lead, Connectivity BU MarvellSanta Clara, CA $182k–$273k2mo Lead end-to-end hardware design and program delivery for advanced optical DSP ASICs serving hyperscale data center, enterprise, and AI infrastructure markets.
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SDE - CPLD / FPGA
AmazonSeattle, Washington, United States
$144k–$194k2mo
Design, implement, verify, validate, deploy, and support programmable logic components (CPLD/FPGA) for AWS server infrastructure to ensure operational excellence and fleet health.
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