ASIC Physical Design
1,648 open positions
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FPGA Lead/Architect/Implementor FlirDenmark - Kongens Lyngby 2mo Lead the architecture, design, and implementation of next-generation ultra-high-speed Ethernet test platforms supporting IEEE802.3dj and Ultra Ethernet standards.
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Sr Principal HW Design Engineer/HW Architect CadenceSAN JOSE $179k–$179k2mo Architect and design hardware system platforms for emulation-acceleration technologies, managing board-level design, schematic entry, PCB layout, and signal integrity.
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AI/ML driven ASIC Design and Implementation Automation Engineer NxpBangalore 2mo Develop prototype AI/ML solutions to improve efficiency and quality (power, performance, area, verification) for SoC and IP development flows.
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Senior Manager, System Co-Design Manager - SCG Team NVIDIAUS, CA, Santa Clara $232k–$232k2mo Lead Product Co-Design and Verification for Speed, Reliability, and Power Compliance in semiconductor design, translating product requirements into silicon solutions.
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Hardware Engineer II ApconHeadquarters 2mo Designing physical electronics for network visibility and switching products, including embedded processors, switch ASICs, and high-speed digital circuitry.
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Senior Design Engineer - IP Office MicrosoftUnited States, California, Mountain View $120k–$120k2mo Lead IP selection, qualification, acquisition, and integration for AI SoC programs, ensuring alignment with product requirements and SoC landing zones.
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IC Digital Design Engineer AumovioBengaluru, KA, in 2mo Architect, design, and verify complex digital front-end circuits and systems for FPGA and ASIC implementations.
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Leader, ASIC Engineering CiscoTaipei, Taiwan 2mo Lead ASIC engineering teams and manage operational relationships with foundry/OSAT partners to deliver high-performance, power-efficient silicon for Cisco's networking platforms.
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Senior DRAM RTL design engineer MicronHyderabad - Phoenix Aquila, India 2mo Design digital IP blocks for DRAM memory solutions from microarchitecture to RTL, covering full-chip integration, verification, and layout.
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Chip Design Engineer, Graviton Chip Design Team
AmazonHaifa, Haifa, Israel
2mo
Define architecture and micro-architecture for a domain within a System-on-Chip (SoC) and write RTL code in Verilog for the AWS Graviton processor family.
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Campus ASIC Engineer (Intern) JumptradingBristol 2mo Design, test, and bring up custom ASIC hardware for ultra-low-latency trading systems using machine learning and algorithms.
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Silicon Domain Architect AlteraSan Jose, California, United States $119k–$119k2mo Define and develop next-generation FPGA silicon architecture, focusing on security technologies, Root of Trust, and hardware/software integration.
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Sr. Formal Verification Engineer, Annapurna Labs
AmazonAustin, Texas, United States
$159k–$159k2mo
Design and optimize hardware for cloud-scale machine learning acceleration, specifically focusing on IP architectures for products like AWS Inferentia.
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Sr. Staff Physical Design Engineer LightmatterMountain View, CA $217k–$217k2mo Implement complex digital blocks for high-performance ASICs in advanced process nodes (3nm), driving timing closure, power integrity, and physical verification for photonics engines.
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DFT (Design For Test) Lead (6251) ItdRemote 2mo Lead the implementation and integration of advanced Design-for-Test (DFT) solutions across the silicon development lifecycle to ensure highly testable, manufacturable, and reliable ASIC designs.
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Principal /Sr. Staff PD Implementation Expert Renesas-ElectronicsBengaluru, KA, in 2mo Drive the complete RTL-to-GDSII physical design flow for next-generation, high-performance System-on-Chips (SoCs), focusing on aggressive Power, Performance, and Area (PPA) metrics.
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Staff Engineer: STA Methodology & Sign-off Lead Enchargeai36India 2mo Architect and lead Static Timing Analysis (STA) methodology and sign-off architecture for large-scale System-on-Chip (SOC) designs to ensure timing convergence and eliminate bottlenecks.
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Hardware Engineer Intern - Summer 2027 ImcChicago $200k–$200k2mo 10-week summer internship focusing on hardware design, algorithm complexity, and RTL programming within a financial trading firm.
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Physical Design Engineer AppleSunnyvale, United States of America 2mo Physical Design Engineer responsible for high-performance PHY design from RTL to GDSII delivery, collaborating with architecture, CAD, timing, and logic teams.
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ASIC Senior Principal Engineer : Design Veirifcation HpeBengaluru, Karnātaka, India 2mo Leads a team of ICs and project teams in the full lifecycle of VLSI design, validation, and testing for complex products and platforms.
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CPU Circuit Design Lead IntelIndia, Bangalore 2mo Leading design analysis and methodologies for memory blocks and data path subsystems in Intel's latest CPU designs.
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Physical Design Engineer - Flow & Methodologies EtchedSan Jose 2mo Architect and maintain automated RTL-to-GDSII physical design flows from first principles to enable rapid iteration and PPA gains for frontier AI inference clusters.
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R&D Engineer BroadcomIND-Bangalore Electronic City - S1 2mo R&D Engineer responsible for physical design, place and route, timing closure, and tapeout integrity checks for top-level-route chips.
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Senior Engineer, Digital Design Engineering AnalogdevicesSpain, Valencia, Cortes Valencianas 2mo Senior Digital Design Engineer responsible for FPGA prototyping, RTL design, and architectural specification of complex SoC blocks for the Intelligent Edge.
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Hardware Development Engineer GraphcoreBristol 2mo Design circuit solutions and validation platforms for Graphcore AI processor systems, turning system requirements into schematics, layouts, and testable hardware.
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ASIC Digital Design Expert (f/m/div) Bosch-GroupRemote 2mo Design digital circuits for advanced Mixed-Signal and System-on-Chip (SoC) ASICs driving leading-edge consumer applications, focusing on MEMS sensor integrated circuits.
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Memory Design Engineer AmbiqmicroincSingapore 2mo Design and validate ultra-low-power embedded SRAM and Register File IPs for advanced SoCs operating in sub-threshold and near-threshold voltage ranges.
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Senior SoC Power Analysis & Optimization Engineer
MatXMountain View (HQ) or Remote
$160k–$160k2mo
Develop and maintain power estimation methodologies, energy models, and perform RTL/gate-level power analysis for AI accelerator SoCs to optimize compute, memory, and interconnect subsystems for AGI workloads.
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