ASIC Physical Design
1,648 open positions
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SoC Static Timing Analysis (STA) Engineer, HBM Micron2 Locations $199k–$199k2mo Own chip-level timing sign-off and drive timing closure for next-generation HBM products across all modes and corners.
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ASIC Design Engineer - Hardware NVIDIAUS, TX, Austin $116k–$116k2mo Define, develop, and deliver system-level IP and methodologies to measure performance on industry-leading GPUs and SOCs.
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Lead Design Engineer CadenceCARY, US 2mo Implement, verify, and achieve timing closure for high-performance hardware-assisted verification SOCs (Palladium and Protium) to support tape-out.
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Senior SoC Power Analysis & Optimization Engineer
MatXMountain View (HQ) or Remote
$160k–$160k2mo
Develop and maintain power estimation methodologies, energy models, and perform RTL/gate-level power analysis for AI accelerator SoCs to optimize compute, memory, and interconnect subsystems for AGI workloads.
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Digital Design RTL Engineer BroadcomUSA-Colorado-Fort Collins-4380 Ziegler Road $122k–$122k2mo Design high-quality SystemVerilog RTL for advanced process nodes (5nm and below), focusing on PPA optimization, CDC/RDC analysis, and low-power design.
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Digital Mixed-Signal System Architect Renesas-ElectronicsAustin, TEXAS, us 2mo Define, model, and validate digital mixed-signal data paths for next-generation digital power management products serving AI, datacenter, and high-performance computing applications.
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Sr. Staff SoC RTL Engineer AmbiqmicroincAustin HQ 2mo Architect, design, and deliver digital hardware for ultra-low-power SoCs and MCUs powering wearables, medical devices, and edge AI applications.
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Principal Silicon Design Engineer MicrosoftIndia, Karnataka, Bangalore 2mo Designing high-performance, high-bandwidth System on Chip (SoC) architectures, RTL, and integration for AI and networking applications.
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FPGA Development Tools Engineer AlteraToronto, Ontario, Canada $100k–$100k2mo Develop and maintain High Level Synthesis (HLS) compiler infrastructure to translate high-level C/C++ code into efficient hardware implementations for FPGA and SoC.
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Timing & Power Analysis CAD Engineer MarvellBangalore 2mo Develop and maintain automated timing and power signoff flows (PrimeTime-STA & PrimePower) within Marvell's M1DP CAD platform for ASIC projects.
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Staff Engineer, Digital Design Engineering AnalogdevicesChina, Beijing, Haidian, Xixiaokou 2mo Lead digital SoC design for high-performance MCU/DSP/NPU products used in automotive smart cockpits and industrial applications.
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Hardware Design Engineer CiscoMilpitas, California, US $136k–$136k2mo Develop high-performance board designs for Cisco's next-generation networking hardware, including high-density access switches, massive-scale service provider routers, and AI infrastructure.
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Internship - Hardware Robustness for SMI Register Interfaces in Automotive PHY Chips NxpEindhoven 2mo Designing hardware-based robustness mechanisms to detect or correct bit errors on the SMI bus and within on-chip register files for automotive PHY chips.
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FPGA研发工程师（J69059） Baidu北京市 2mo Design and develop high-performance gateway hardware, including logic design, architecture, and programming.
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Digital Designer ON SemiconductorRoznov pod Radhostem, Vsetin, Czech Republic 2mo Design and verify digital circuits and architectures for next-generation driver devices and SoC solutions.
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3D Stacked DRAM-on-Logic Design Engineer SkhynixamericaSan Jose, CA $150k–$150k2mo Design and optimize digital IP and SoC for 3D-stacked DRAM-on-Logic systems to enable advanced memory solutions for customers.
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Sr. Engineer, RTL Implementation TenstorrentSanta Clara $100k–$100k2mo Iterating front-end CAD flows on multiple process technologies to refine CPU core configurations and optimize Power, Performance, and Area (PPA) for a RISC-V based CPU.
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Static Timing Analysis Engineer IntelIndia, Bangalore 2mo Physical Design Timing Engineer ensuring optimal performance and efficiency for Intel's next-generation SoCs in high-performance computing and AI.
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SoC Interconnect Technology Team Lead ArmSophia Antipolis, France 2mo Lead architecture, design, and execution of next-generation coherent and non-coherent interconnect solutions for advanced SoCs, focusing on performance, power efficiency, and system-level optimization.
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Senior Physical Design Engineer MediaTekAustin, TX 2mo Drive Advanced Place & Route (APR) and physical verification (PV) signoff for high-performance CPU cores in 3nm and other leading-edge technology nodes.
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System Architect, Custom Silicon GlobalFoundriesRichardson $171k–$171k2mo Lead end-to-end system architecture development for complex semiconductor products (ASICs, SoCs, MCUs, networking, automotive, aerospace) from concept through production.
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Principal SoC Architect AptivUSA Walnut Creek, CA - WR $168k–$168k2mo Lead a team of semiconductor engineers to define SoC architecture specifications, select IP, and manage external design partners for custom silicon used in autonomous driving and connected vehicle systems.
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