ASIC Physical Design
1,645 open positions
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Digital IC Design/Verification Engineer↗ Marvell TechnologyCordoba, Córdoba, Argentina 1mo Implementing digital logic blocks for high-speed coherent transceivers in PCIe systems, including RTL design, verification, and automated test case development.
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FPGA Developer (f/m/x) ZeissgroupOberkochen 1mo Design and implement FPGA-based digital logic, develop custom IP cores, and optimize designs for timing, power, and performance.
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Principal Engineer - Digital Design↗ Microchip Technology Inc.Cork, County Cork, Ireland 1mo Designing high-performance multi-gigabit T1 Ethernet PHYs and digital blocks for automotive and industrial networking ICs.
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Interconnect Design Engineer SiFive4 Locations $140k–$140k1mo Designing industry-leading CPU and interconnect IP (TileLink, cache controllers, protocol bridges) as highly-configurable generators using Chisel/Scala to accelerate RISC-V SOC adoption.
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Principal HW System Architect (f/m/d) Renesas-Electronics's-Hertogenbosch, NB, nl 1mo Translate customer and standardization requirements into state-of-the-art SoC architectures and detailed target specifications for connectivity chips.
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Concepteur Digital Design (H/F/N) Bosch-GroupValbonne, Provence-Alpes-Côte d'Azur, fr 1mo Digital design engineer developing SoC/ASIC subsystems and IP for automotive applications.
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Digital Design Engineer I SilabsAustin $79k–$79k1mo Design and develop digital components and SoC architectures for wireless microcontroller products.
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SoC Power Analysis and Optimization Engineer AppleBeaverton, United States of America 1mo Drive SOC power simulation, optimization, and modeling to improve power efficiency and provide projections for future projects.
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Senior Engineer BroadcomIND-Bangalore Electronic City - S1, IN 1mo Senior IC physical design engineer responsible for block-level floor-planning, partitioning, placement, clock tree synthesis, routing, and physical verification to meet congestion, timing, and area metrics.
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Mid-level Physical Design Engineer CPU IntelUS, Oregon, Hillsboro $122k–$122k1mo Execute physical design implementation for CPU core blocks or subsystems within the RTL-to-GDS flow, contributing to high-performance, power-efficient silicon.
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ASIC/SOC DFT Engineer (Silicon Engineering) SpaceXAustin - 800 1mo Developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures to enable global connectivity.
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Senior PD Engineer: Synthesis & STA Enchargeai36Remote 1mo End-to-end ownership of logic synthesis and quality signoff for key blocks and sub-chips, acting as a bridge between front-end design and back-end physical implementation teams.
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Technical Program Manager, Silicon AnthropicSan Francisco, CA $365k–$365k1mo End-to-end execution of custom silicon development for Claude AI models, from architecture definition through tapeout and production ramp.
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Director- R&D Technical Head SemtechIND - Hyderabad 1mo Define and own end-to-end chip design strategy, methodology, and technology roadmap across SoC, Analog, Digital, Product & Test Engineering, Design Packaging, Verification, and DFT verticals.
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STAFF ASIC Design Engineer MicronHsinchu - Chang Yih, Taiwan 1mo Design, implement, and debug complex logic for next-generation solid-state drive controllers, covering RTL development, integration, and validation from concept to production silicon.
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Timing Engineer AlteraSan Jose, California, United States $119k–$119k1mo Lead timing activities for FPGA subsystems, achieving timing convergence from implementation through final sign-off.
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Host and Network IO FPGA Engineer CerebrasHeadquarters/Sunnyvale Office 1mo Design and implement the full in-chassis IO subsystem for Cerebras' AI chip, connecting distributed server nodes via custom RoCE v2 networks to the WSE.
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Senior Manager, ASIC Chip Engineering NVIDIAUS, CA, Santa Clara $232k–$232k1mo Drive development of future SoC processors for client, workstation, embedded, and automotive markets from concept to production.
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Hardware Engineer (Enterprise Switch) UbiquitiTaipei 1mo Lead hardware circuit design, schematic capture, and layout review for next-generation, high-density, and high-throughput networking platforms.
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Director, Physical Design (Silicon One) CiscoSan Jose, California, US $251k–$251k1mo Lead the physical design implementation of complex SoCs for Cisco's Silicon One architecture, optimizing PPA goals and managing execution schedules for advanced process nodes.
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Senior Staff Hardware Engineer MarvellTaipei 1mo Design high-performance board-level systems for storage, network security, and custom ASIC applications, managing designs with JDM partners to ensure production quality.
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Physical Design Engineer Intern MonolithicpowerBarcelona, Spain 1mo Assist in the development, design, and physical implementation of digital and mixed-signal ICs utilizing leading edge technologies.
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Physical Design Methodology Engineer, AI HW IP TenstorrentAustin $100k–$100k1mo Develops, deploys, and owns the RTL-to-GDSII methodology for AI hardware IP physical design teams to ensure new blocks start from a working flow.
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SoC Architect WaymoMountain View (US-MTV-EMF690) $251k–$251k1mo Architect and create high-performance custom silicon and system-level compute architectures for Waymo's fully autonomous vehicle software stack.
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Senior FPGA Engineer, Cyber AndurilindustriesWashington, DC (999) $166k–$166k1mo Design and implement high-throughput FPGA datapaths, packetization pipelines, timing-sensitive interfaces, and hardware-near acceleration blocks for offensive cyber missions.
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Principal AI Silicon Architect MicrosoftUnited States, California, Mountain View 1mo Define high-performance silicon architecture specifications for AI accelerators and guide end-to-end silicon development cycles.
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Physical Design Engineer AxiadoHyderabad, TS, in 1mo Backend implementation engineer responsible for floorplanning, placement, CTS, routing, timing closure, and physical signoff for ASIC chips.
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Principal Engineer PD AsteralabsSingapore City 1mo Senior Physical Design Engineer developing next-generation transceiver IPs for high-speed connectivity in advanced technology nodes.
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2027校招 - 数字IC设计工程师 / Digital Design Engineer Texas InstrumentsShanghai, China 1mo Architect new TI products by defining, designing, modeling, and verifying digital circuits including 64-bit DSP processors, MMUs, and heterogeneous multicore shared memory/cache systems.
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Principal SoC Chip Lead NxpShanghai (Pudong), CN 1mo Own SoC program execution from project definition through tape-out and post-silicon support, ensuring on-time delivery and coordinating engineering support during silicon bring-up and validation.
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Hardware Engineer (FPGA/ASIC) JanestreetLondon 1mo Intern role focused on using programming language technology (OCaml/Hardcaml) to improve the design, testing, and validation of hardware designs.
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Digital Design Engineer – AI Accelerators StmicroelectronicsGreater Noida, India 1mo Design and implement high-throughput compute datapaths and microarchitectures for AI accelerator chips, integrating compute blocks with memory interfaces.
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