ASIC Physical Design
1,650 open positions
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SOC Timing Analysis (STA) Engineer ,HBM MicronRichardson, TX 3mo Own chip-level static timing sign-off and methodology development for next-generation High Bandwidth Memory (HBM) dies in sub-5nm nodes.
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ASIC DFT STA Technical Lead Cisco2 Locations $169k–$169k3mo Lead Static Timing Analysis (STA) and Design for Test (DFT) for next-generation networking ASICs, ensuring timing closure and quality across implementation and post-silicon phases.
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Compute Subsystem Architect MediaTekSan Jose, CA 3mo Define and build compute subsystem capabilities for next-generation ASIC and advanced Arm computing platform products, covering core configuration, cache architecture, and interconnect topology.
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Digital Design Engineer AccentureBengaluru 3mo Design and implement digital circuits and systems with a focus on logic, timing, and power optimization.
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Digital IC Design Engineer Texas InstrumentsDallas, TX, United States 3mo Design and verify digital logic for next-generation power management and analog ICs serving industrial, automotive, and consumer applications.
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Senior ASIC Hardware Design Engineer NVIDIAIsrael, Beer Sheva 3mo Design and implement high-performance, low-power security engines and RISC-V processor modules for NVIDIA's CPU and SoC product lines.
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Hardware Design Engineer PurestorageOffice - Taipei (Taiwan) 3mo Architect and launch next-generation high-performance solid-state storage solutions from concept to global mass production, focusing on high-speed hardware interfaces to reduce TCO and energy consumption.
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Principal Design Engineer - Physical Design CadenceSHANGHAI 3mo Lead high-speed digital DDR PHY IP physical implementation and optimize design flows for cutting-edge semiconductor processes.
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Principal Engineer, Automated Derivatives Renesas-ElectronicsRemote 3mo Lead end-to-end delivery of derivative System-on-Chips (SoCs) by building an AI-augmented 'Silicon Factory' that uses machine learning to bridge architectural intent and GDSII, focusing on ultra-fast turnaround times.
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Hardware Engineer ImcChicago $200k–$200k3mo Design and verify custom ASICs for low-latency trading infrastructure, collaborating with software and research teams to solve complex hardware challenges.
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Principal System Engineer NxpCaen, FR 3mo Lead architectural definition, design, and implementation of complex embedded systems for next-generation semiconductor products.
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Manager, Design Verification AnalogdevicesCLOSED-India, Bangalore, Aveda Meta 3mo Lead physical design implementation for complex block- and top-level SoCs, ensuring timing closure, power integrity, and signoff quality while leading a small engineering team.
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Senior Principal System Architect ArmSan Jose, California $323k–$323k3mo Define and explore next-generation system architectures and technologies for compute infrastructure across data center and networking domains.
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ASIC / Digital Design Director of Engineering ON SemiconductorBangalore, Karnataka, India 3mo Lead development of next-generation Automotive Networking solutions including SerDes, Ethernet, and high-speed communication SoCs.
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Senior Engineer, SoC Architecture – Memory Subsystem and Interconnect SamsungresearchamericaMountain View, CA $159k–$159k3mo Architecting next-generation SoC Fabric, System Cache, and DRAM Controller subsystems to optimize power, performance, and area for Samsung Galaxy devices.
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FPGA IP Software Development Engineer AlteraBengaluru, Karnataka, India 3mo Design, develop, and validate high-performance FPGA Soft IP solutions from micro-architecture definition through physical hardware validation.
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Senior Engineer, FPGA AmbiqmicroincSingapore 3mo Develop and render FPGA images for pre-silicon prototyping environments to support SoC design, verification, and system test teams.
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逻辑工程师 SicarrierChina / Guangdong-Shenzhen,China / Shanghai-Shanghai,China / Hubei-Wuhan,China / Zhejiang-Hangzhou 3mo Conducts industry research and architecture design for FPGA/ASIC hardware systems, focusing on processor, memory, wireless, and AI innovations.
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SoC Machine Learning Design Engineer AppleAustin, United States of America 3mo Designing machine learning solutions to optimize efficiency, quality, and speed for Apple's SoC chip design process, specifically in RTL Design, Verification, and Power/Performance/Area efforts.
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Modelling Lead (SystemC / Virtual-Platform Architect) LumilensSan Jose 3mo Build executable SystemC/TLM-2.0 virtual platforms and architecture models for pre-silicon firmware bring-up and design-space exploration for photonic AI supercomputing engines.
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Senior Quantum Engineer - Digital Control Systems MicrosoftUnited States, Washington, Redmond 3mo Design and implement digital control subsystems interfacing with cryogenic hardware and ASICs for real-time control and feedback of quantum systems.
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ASIC Design Engineer HpeBengaluru, Karnātaka, India 3mo Define and architect high-performance blocks for next-generation networking ASICs, optimizing throughput and power efficiency.
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Senior RTL Engineer, Interconnect Design OpenAISan Francisco 3mo Designing and delivering critical on- and off-chip interconnect components (NoC, switches, routers, protocol bridges) for custom AI accelerator platforms to power frontier models.
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