ASIC Physical Design
1,645 open positions
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Digital IC Design Engineer | Custom Texas InstrumentsDallas, TX, United States 2mo Designing digital and mixed-signal circuits for custom ASSP ICs for a marquee customer.
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Member of Technical Staff, SoC Power and Physical Architect, Next-generation HBM Architecture MicronFolsom, CA $191k–$191k2mo Drive SoC-level specification for 3D-stacked, high-performance high-bandwidth memory (HBM) architectures, focusing on power, physical planning, and early SoC design activities.
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Technical Program Manager, Hardware Chips Development OpenAISan Francisco 2mo Managing the design and implementation planning of ML acceleration hardware and chip hardware roadmaps for OpenAI's supercomputers.
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Graduate Talent (CPU-SoC Silicon Design) IntelMalaysia, Penang 2mo Design and develop next-generation SOC/CPU for Intel products, focusing on RTL validation, structural physical design, analog IP, and system integration.
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Digital Physical Design Engineer NxpNoida 2mo Drive timing closure, fix setup/hold violations, and optimize designs for performance and area using Synthesis, Place & Route (PnR), and Static Timing Analysis (STA).
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Sr. Physical Design Engineer LumilensSan Jose 2mo Senior Physical Design Engineer owning full-chip and block-level physical implementation from RTL to GDSII for high-performance ASICs in advanced TSMC nodes (5nm/3nm).
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Principal ASIC Chip Design Engineer NVIDIAIsrael, Tel Aviv 2mo Establish ASIC design methodologies, develop shared code, and drive adoption of new technologies to ensure efficient chip design operations.
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) SpaceXAustin - 800 $175k–$175k2mo Developing cutting-edge next-generation silicon for deployment in space and ground infrastructures to enable global connectivity via the Starlink network.
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Senior Performance Architect MicrosoftUnited States, Oregon, Hillsboro 2mo Develop performance modeling methodologies and analysis tools for System on Chip (SOC) and Intellectual Property (IP) to identify bottlenecks and justify architectural changes.
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Senior Digital Engineer Renesas-ElectronicsChandler, Arizona, us 2mo Architect, design, and integrate low-power digital circuits for mixed-signal data conversion and power management products in advanced process nodes.
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Spécialiste FPGA - Aéronautique (F/H) AltenBordeaux, Nouvelle-Aquitaine, fr 2mo Develop and validate complex FPGA/SOC designs for critical embedded aerospace applications (video systems, flight computers, energy management) ensuring reliability and DO254 compliance.
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SoC Physical Design Engineer - Power Delivery AppleWaltham, United States of America 2mo Designing and automating the physical implementation of power delivery networks within System-on-Chip (SoC) architectures.
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Senior Engineer-STA ArmBengaluru, India 2mo Developing and validating timing constraints and performing timing analysis/closure for System-on-Chip (SoC) and block/subsystem levels.
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Senior Physical Design Engineer Cisco2 Locations 2mo Lead backend VLSI design flow development from RTL to GDS, handling definition, physical synthesis, place and route, optimization, timing closure, and floor planning for high-quality ASIC designs.
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Principal Engineer, Digital Design (IO Subsystem) ON SemiconductorAllen, TX, United States 2mo Architecting and delivering a highly configurable IO subsystem for onsemi's microcontroller platform to enable scalability and product differentiation.
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Staff Engineer, Physical Design SiFiveBengaluru, Karnataka, India 2mo Drive end-to-end physical design implementation (Synthesis, Floorplanning, P&R, Signoff) for next-generation IPs, translating complex RTL into high-performance silicon while optimizing Power, Performance, and Area (PPA).
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ASIC SoC System Architect, Lund AxisSweden - Lund 2mo Define system-level architecture and requirements for ARTPEC SoC chips, selecting third-party IPs and collaborating with RTL design, verification, and ASIC vendor teams to deliver security features for IoT ecosystems.
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Director, Silicon Logical Design GraphcoreBristol 2mo Lead and scale the Logical Design group to define micro-architecture and RTL for Graphcore's AI compute chips, ensuring world-class performance, power, area, and schedule.
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Senior Hardware Design Engineer, Ethernet Switching Arista-NetworksRoseville, CA, us $162k–$162k2mo Designing high-speed Ethernet switching hardware for AI clusters, data centers, and enterprise campuses.
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Lead Engineer (IP Design & Microarchitecture) Siemens-EdaNoida, IND, India 2mo Designing low-power custom hardware accelerators and optimizing IP for Power, Performance, and Area (PPA) in Electronic Design Automation (EDA) tools.
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Chip Design Engineer, Nitro Team
AmazonTel Aviv-Yafo, Tel Aviv, Israel
2mo
Design and develop micro-architecture and RTL for the AWS Nitro SoC, integrating into millions of servers worldwide.
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Physical Design Technical Lead AlteraSan Jose, California, United States $210k–$210k2mo Own complex SOC and block-level implementation challenges end-to-end, from floorplan and power intent through final signoff, while shaping ML/AI-driven implementation flows.
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