ASIC Physical Design
1,650 open positions
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Staff Digital IC Design Engineer ON SemiconductorMarin-Epagnier, Neuchatel, Switzerland 2mo Architect, specify, implement, simulate, and benchmark embedded MCU/DSP systems and hardware accelerators for semiconductor products.
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Career Accelerator Program - Digital Design Engineer Texas InstrumentsTucson, AZ, United States 2mo Architect new TI products by defining, designing, modeling, and verifying digital circuits including 64-bit DSP processors, MMUs, and multicore shared memory systems.
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STA Lead (m/f/d) AppleMunich, Germany 2mo Leading a local team responsible for SoC design timing and synthesis, ensuring timing closure from synthesis to sign-off for Analog Mixed Signal IPs.
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Hardware Engineer- HW Board Design CiscoCaesarea, Israel 2mo Design and develop hardware boards for next-generation networking chips and AI infrastructure devices.
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Chip Design Engineer, Nitro Team
AmazonTel Aviv-Yafo, Tel Aviv, Israel
2mo
Design and develop micro-architecture and RTL for the AWS Nitro SoC, integrating into millions of servers worldwide.
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Graduate CPU Physical Implementation Engineer ArmSophia Antipolis, France $45k–$47k2mo CPU Physical Implementation Engineer optimizing frequency, power, and area metrics for next-generation processors at 3nm nodes.
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High Speed Interface Protocols, Principal AE CadenceSAN JOSE $123k–$123k2mo Architect high-speed interface solutions for customers using Cadence Serdes IP and showcase performance to win business opportunities.
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IP Design Architect NxpAustin (Oakhill, Office) 2mo Define and develop graphics, display controller, and RISC-V IP architectures and designs for next-generation products.
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Physical Design Technical Lead AlteraSan Jose, California, United States $210k–$210k2mo Own complex SOC and block-level implementation challenges end-to-end, from floorplan and power intent through final signoff, while shaping ML/AI-driven implementation flows.
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DFx Engineer Samsung Electronics3900 N Capital of Texas Hwy, Austin, TX, USA $180k–$180k2mo Architecting and implementing Design for Test (DFT) scan solutions for high-performance digital IP (CPU/GPU) and System-on-Chip (SoC) projects to ensure high test coverage and yield.
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Design Engineer LumilensSan Jose 2mo Design and implement digital front-end RTL blocks, including high-speed datapaths for UCIe and optical front-end interfaces.
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Senior Customer Release Engineer SiFiveBengaluru, Karnataka, India 2mo Ensuring SiFive IP customer deliverables are integrated, validated, and delivered on time with high quality for chip design applications.
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Architecture ASIC Engineer MarvellCordoba, Argentina 2mo Design, simulate, and validate DSP ASICs for coherent optical communications systems serving Data Center interconnect and Long Haul/Metro markets.
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Senior Design Engineer - Memory Subsystem NVIDIAIndia, Bengaluru 2mo Designing state-of-the-art memory subsystem components for industry-leading GPUs and SOCs used in consumer graphics, self-driving cars, and AI.
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Physical Design Engineer
AmazonTel Aviv-Yafo, Tel Aviv, Israel
2mo
Developing semiconductor platforms and next-generation cloud products using revolutionary system architectures.
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Logic Lead FlirIndia - Pune 2mo Architectural design and FPGA implementation of next-generation wireless protocol analyzers to capture, demodulate, and process high-speed RF signals.
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ASIC Design Engineer HpSingapore, South West, Singapore 2mo Design and verify digital ASIC components for inkjet and laserjet printing systems, supporting design implementation, silicon validation, and system integration.
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Product Engineer Siemens-EdaNew Cairo, EGY, Egypt $24k–$24k2mo Support the definition, promotion, and deployment of hardware-assisted acceleration using Veloce proFPGA CS prototyping solutions for semiconductor and systems customers.
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Senior Member of the Technical Staff GlobalFoundriesHsinchu 2mo Senior technical leadership role driving the development and delivery of high-performance compute processor IP solutions.
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E-Core (Atom) CPU Layout Design Engineer IntelMalaysia, Penang 2mo Design physical implementation of memory compilers, custom IP blocks, and layout partitions for Intel Atom microprocessors.
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Chip Design Engineer
AmazonTel Aviv-Yafo, Tel Aviv, Israel
2mo
Designing and delivering high-end custom silicon for AWS cloud infrastructure, specifically the Nitro platform.
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ASIC Design Engineer HpeBengaluru, Karnātaka, India 3mo Architecting and designing high-performance blocks for advanced networking ASICs to deliver maximum throughput with minimum power.
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EDA flow and Logic Synthesis Engineer (Senior Engineer)↗ Synopsys IncDublin, County Dublin, Ireland 3mo Develop, run, and support mid-end flows spanning synthesis, DFT, static checking, formal equivalence, and power analysis to convert RTL outputs into clean, implementation-ready inputs for physical design.
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Chip Design Engineer, Graviton Team
AmazonTel Aviv-Yafo, Tel Aviv, Israel
3mo
Design and develop semiconductor processors (SoC) for cloud infrastructure, driving architecture from definition through tape-out.
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R&D Engineer IC Design 4 BroadcomUSA-CA San Jose Innovation Drive $122k–$122k3mo Front-end design and verification of design blocks for ASIC cores, translating system requirements into logic and ensuring timing closure.
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Senior FPGA Mixed Signal Engineer AnalogdevicesFrance, Sophia-Antipolis 3mo Design and develop FPGA-based solutions for mixed-signal systems and evaluation platforms, focusing on Xilinx Zynq devices.
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Senior FPGA Design Engineer AnellophotonicsSanta Clara, CA 3mo Lead FPGA-based hardware development for integrated photonic system-on-chip and AI technology for next-generation navigation in GPS-Denied environments.
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Principal ASIC Physical Design Engineer K2spacecorporationSeattle $190k–$190k3mo Lead the implementation of complex SoCs for next-generation satellite and space systems, owning the full physical design flow from RTL handoff to GDSII.
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EE 硬體研發工程師 - Server (ACG/ 林口園區) AdvanTechLinkou 3mo Design and validate server system hardware for x86 platforms, focusing on high-speed interfaces and power management.
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Staff Design Engineer MicronSan Jose, CA $145k–$145k3mo Designing and verifying digital circuits for NAND memory products, optimizing performance, area, and power targets.
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SoC System Architect (Smart Home/Personal Device) MediaTekChuPei 3mo Evaluating technical feasibility and defining architectural direction for new SoC products prior to project kickoff.
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Senior FPGA Engineer (Algo) DrwengChicago $150k–$150k3mo Architect and implement low-latency, high-throughput FPGA applications from scratch for a diversified trading firm's trading teams.
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Hardware Design Integrity Engineer Arista-NetworksSanta Clara, CA, us $130k–$130k3mo Debugging production system problems and delivering root cause analysis and fixes for high-speed networking hardware.
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