ASIC Physical Design
1,643 open positions
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ASIC Product Development Team Lead MicronSan Jose, CA $206k–$206k3mo Leading end-to-end execution of ASIC/SoC product development from specification through silicon bring-up and production.
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CPU Performance – Principal Microarchitecture Exploration Engineer ArmMultiple locations $250k–$250k3mo Define and design next-generation CPU microarchitecture for Arm's Cortex-X and Neoverse CPUs, focusing on performance, power, and area efficiency.
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ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs
AmazonCupertino, California, United States
$157k–$213k3mo
Design and optimization of custom hardware (ASICs) for AWS Machine Learning inference servers, specifically the Inferentia chip.
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<Data center>DFT Senior Engineer MediaTekHsinChu 3mo Leading DFT task force and implementing DFT flows for cloud data center products.
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Senior Engineer, GPU Modeling Architect Samsung Electronics3655 N 1st St, San Jose, CA, USA $124k–$124k3mo Design and development of high-performing functional models for next-generation Samsung GPUs, enabling architectural exploration and design decisions.
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PMTS Application Engineering GlobalFoundriesSeoul 3mo Field Application Engineer supporting customer engagements in Korea to enable design wins by bridging customer requirements with MIPS' processor IP, software tools, and custom silicon solutions.
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Principal Engineer BroadcomChina-Shanghai-Zhangjiang Hi Tech 3mo Lead ASIC design and implementation for 5nm/3nm CMOS cell-based solutions, managing the full development lifecycle from RTL analysis to post-prototype test support.
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Staff Engineer, Design Enablement Renesas-ElectronicsRemote 3mo Define and deploy physical design methodologies for advanced SOCs and MCUs across 3/5/16/22nm nodes.
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Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
AmazonCupertino, California, United States
$157k–$157k3mo
Design and optimization of hardware for data centers, specifically focusing on machine learning inference products like AWS Inferentia.
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Sr. SoC Power Engineer, Annapurna Labs - Cloud Scale Machine Learning
AmazonCupertino, California, United States
$183k–$248k3mo
Modeling and estimating power consumption for machine learning accelerator SoCs (Inferentia and Trainium) from RTL to netlist stages.
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Senior/Principal Physical Design Engineer FractileThe Crescent 3mo End-to-end implementation of complex IC physical designs from synthesis to sign-off to increase clock speed for AI inference systems.
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Team Leader - Digital IC design AumovioBengaluru, KA, in 3mo Leading a digital IC design team in Bangalore, coordinating resources and processes for automotive product development.
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ASIC Design Engineer HpeBengaluru, Karnātaka, India 3mo Define and architect high-performance blocks for advanced networking ASICs, performing micro-architecture and logic design to maximize throughput while minimizing power.
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Physical Design Engineer II (PNR/Physical Verification/STA/EMIR) CadenceTORONTO 02, CA 3mo Physical Design Engineer responsible for implementation, timing closure, and signoff in advanced technology nodes.
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Debug/Trace/Profiling Design Engineer SiFiveLa Ciotat, France 3mo Designing industry-leading debug, trace, and profiling IP for RISC-V processor cores to enable high-performance SOC designs across AI, automotive, and data center markets.
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System IC Architect - Advanced Power Systems NxpRemote 3mo Define next-generation Point of Load (PoL) power solutions and System-in-Package (SiP) architectures for high-performance core power in automotive and AI compute platforms.
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Senior Digital Design Engineer for Korea ISG ON SemiconductorSeoul, Korea, Republic of 3mo Designing CMOS image sensors from RTL to chip for consumer and automotive sensor solutions.
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Manager, Physical Design Circuit and Signoff CAD NVIDIAIsrael, Yokneam 3mo Lead a team responsible for tracking and executing end-to-end activities spanning internal CAD flow development and circuit-level studies to support silicon sign-off for NVIDIA's advanced chips.
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Digital Senior Design Engineer CienaOttawa $109k–$109k3mo Design power and area optimized functional blocks for Ciena's Wavelogic optical fiber transmission products.
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Principal NoC IP Micro-Architect AlteraPenang 15, Penang, Malaysia 3mo Designing logic, RTL coding, and simulation for Network on Chip (NoC) IPs and FPGA subsystems for full chip integration.
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Staff/Senior Staff Physical Design Engineer (Technical Lead) Enchargeai36Remote 3mo Lead physical design for next-generation in-memory computing silicon products, optimizing PPA for edge-to-cloud applications.
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CAD Engineer - Static Timing Analysis & Physical Design AppleHaifa, Israel 3mo Develop and support advanced Static Timing Analysis (STA) flows and methodologies to deliver robust timing closure solutions for cutting-edge silicon designs.
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Micro-Architect and RTL Designer
MatXMountain View (HQ) or Remote
$160k–$160k3mo
Designing high-performance silicon micro-architecture and RTL for compute, memory management, and high-speed connectivity blocks to support AGI workloads.
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Staff Engineer, Digital Design Engineering AnalogdevicesIndia, Bangalore, RMZ 3mo Lead the development, curation, and delivery of reusable strategic digital IPs (accelerators, datapath, high-speed interfaces) to accelerate product development across business units.
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EDA Tools Hardware Engineer IntelUS, California, Santa Clara $142k–$142k3mo Develop and maintain full-chip physical implementation flows, including floor planning, hierarchical block integration, placement, routing, power grid planning, and clock tree synthesis to enable scalable SoC assembly.
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