ASIC Physical Design
1,647 open positions
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Senior Staff/ Staff Design Engineer SilabsSingapore 4mo Designing digital blocks and SoC infrastructure for low-power MCU and Wireless products.
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Senior Physical Design Methodology Engineer, PPA Fusion Compiler NVIDIAUS, CA, Santa Clara $168k–$168k4mo Developing efficient physical design methodologies and ML-based solutions for high-speed communication devices and graphics processors to optimize Power, Performance, and Area (PPA).
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Senior Staff Engineer, Physical Design - NoC SiFiveBengaluru, Karnataka, India 4mo Own and drive the implementation of massive, high-bandwidth interconnects (NoC) and Uncore subsystems from RTL to GDSII, acting as a bridge between architecture and physical design to optimize PPA.
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PD Intern EtchedSan Jose 4mo Realizing front-end designs in silicon to improve iteration speed to final signoff for inference-focused AI hardware.
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High‑Speed RTL Design Engineer MicronBengaluru, India 4mo Design and implement timing-critical RTL blocks for high-speed memory and storage solutions, ensuring robust logic for synthesis and timing closure.
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SOC Micro-Architect and RTL Designer
MatXMountain View (HQ) or Remote
$160k–$160k4mo
Designing high-performance silicon micro-architecture and RTL for compute, memory management, and high-speed connectivity subsystems for AGI training workloads.
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IP RTL Design Engineer Samsung ElectronicsSSIR, Goldstone, Bangalore, India 4mo Develop high-performance PHY IP for HBM and LPDDR memory interfaces, focusing on RTL design, verification, and post-silicon support.
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SoC/IP Architect Texas InstrumentsBengaluru, Karnataka, India 4mo Define and document SoC architecture including system topology, IP selection, and integration strategy for complex mixed-signal MCUs.
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<GPU>GPU IC Design and Integration Engineer MediaTekHsinChu 4mo GPU IC design and integration focusing on digital design flow, low power analysis, and post-silicon debugging.
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PCIe design Architect BroadcomIND-Bangalore Electronic City - S1 4mo Designing and architecting PCIe subsystems and SoCs for Broadcom products.
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Senior Hardware Design Engineer, High Speed Networking Arista-NetworksNashua, NH, us 4mo Designing high-speed networking and Ethernet products for enterprise campuses, hyperscale datacenters, and AI clusters.
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ASIC Design Engineer AppleSanta Clara, United States of America 4mo Designing memory subsystems and highly interconnected system architectures for Apple hardware products.
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Senior Staff ASIC Design Engineer AxiadoHyderabad, TS, in 4mo Design and implement System-on-Chip (SoC) micro-architecture, RTL coding, synthesis, and timing closure for secure AI infrastructure.
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AMBA Architect ArmCambridge, United Kingdom 4mo Designing next-generation Arm system architectures focusing on memory systems, address translation, and virtualization-aware interfaces.
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Staff Digital IC Design Engineer AnalogdevicesSingapore, Kallang 4mo Designing and implementing digital ICs and micro-architectures for Optical Control ICs serving AI datacenters.
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Senior/Staff Digital Design Engineer OlixAustin, TX 4mo Architect, design, and implement high-throughput digital pipelines for real-time data-processing silicon in advanced CMOS nodes.
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Senior ASIC Design Engineer – Processor Subsystem EspaceSaratoga, CA 4mo Design, configuration, integration, and verification planning of Arm processor IP and associated subsystem components for satellite IoT connectivity ASICs.
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Principal System Engineer (f/m/d) Renesas-ElectronicsRemote 4mo Define and drive the system architecture of next-generation sensor IC solutions for automotive and industrial markets, translating system requirements into silicon architectures.
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Principal Hardware Engineer HpeSunnyvale, California, United States of America $154k–$311k4mo Design, analyze, develop, and evaluate electrical/electronic parts, components, sub-systems, and integrated circuitry for high-end routing platforms from concept to mass production.
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