ASIC Verification Engineering
1,076 open positions
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Staff/ Principal Design Verification Engineer AsteralabsTel Aviv 2mo Develop ASIC verification environments and testbenches to validate high-performance digital blocks, subsystems, and full-chip designs for next-generation AI connectivity silicon.
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AMS Verification Engineer (all gender) AltenRemote 2mo AMS verification of I/O interfaces, defining verification strategies, developing testbenches, executing simulations, and debugging functional, electrical, and timing issues.
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ASIC Verification Engineer NVIDIAUS, CA, Santa Clara $116k–$116k2mo Own validation of Clocking structures in Tegra and GPU products from start to finish, including test plan development, automation, validation flows, coverage metrics, and bug identification.
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ASIC Engineering Technical Leader CiscoBangalore, India 2mo Lead a team of test engineers to develop, validate, and optimize production test solutions (ATE) for Cisco's next-generation ASIC and SoC products from NPI through high-volume production.
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Senior Staff Engineer, GPU Design Verification (Subsystems) Samsung Electronics3655 N 1st St, San Jose, CA, USA $180k–$180k2mo Senior Staff Engineer responsible for verification strategy and hands-on validation of complex GPU subsystems for next-generation mobile GPUs, ensuring functional correctness and performance integrity.
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Sr Principal Design Engineer CadenceSAN JOSE $154k–$154k2mo Senior Solutions Engineer developing hardware emulation and FPGA prototyping platforms for semiconductor customers, bridging R&D and customer needs to solve complex high-speed protocol challenges.
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CPU Verification Engineer IntelUS, Texas, Austin $106k–$106k2mo Develop and execute verification plans to validate CPU logic against architectural specifications for next-generation processors.
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FPGA Engineer Sapsol-Technologies-IncMelbourne, Florida, United States 2mo Develop RTL designs, verification environments, and hardware lifecycle management for FPGA/ASIC products.
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ASIC Verification Engineer BroadcomUSA-CA Irvine Alton Parkway Bldg 2 $101k–$101k2mo Develop verification environments and testbench components for high-speed interconnect ASICs (100Gbps to 400Gbps) using SystemVerilog UVM, collaborating with architecture and firmware teams.
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Graphics Cache Hierarchy Design Verification Engineer AppleSanta Clara, United States of America 2mo Pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory Management Unit, Interconnects, and Link interface units for high-performance, power-efficient processors.
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Principal Modem PHY IP Design Verification Engineer - Terawave BlueoriginCentral Texas, US $269k–$269k2mo Lead verification of advanced modem PHY IP for next-generation wireless ASIC platforms within the Terawave satellite communications network.
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CPU Verification Engineer, Verification Team
AmazonHaifa, Haifa, Israel
2mo
Verifying the correctness, performance, and robustness of next-generation ARM CPU cores and their surrounding subsystems before silicon production.
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Senior PCIe IP Design Verification Engineer MicrosoftUnited States, Oregon, Hillsboro 2mo Lead verification of complex Peripheral Component Interconnect Express (PCIe) Bridge IP flows, defining strategies and test plans to ensure quality.
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Staff Verification Design Engineer, DRAM MicronBoise, ID - Main Site 2mo Design and drive verification strategies for Micron's leading-edge DRAM memory products, ensuring performance, quality, and reliability from gate-level to full chip.
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Senior Lead Engineer - SoC Design Verification NxpPune 2mo Architect, develop, and maintain UVM-based and C-based verification environments for RTL functional verification of in-vehicle networking devices.
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Staff Engineer - Design Verification AmbiqmicroincSingapore 2mo Design Verification Engineer responsible for verifying digital and mixed-signal SoC designs for low-power IoT and AI edge applications.
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Design Verification Engineer | Sensing Texas InstrumentsDallas, TX, United States 2mo Develop and execute verification plans and SystemVerilog testcases for advanced mixed-signal sensor circuits and high-performance digital circuits interfacing with analog circuitry.
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Senior engineer ArmMultiple locations 2mo Verify RTL implementing upcoming features in ARM SoC to ensure new functionality and existing features meet architectural requirements.
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Staff Mixed-Signal Verification Engineer Renesas-ElectronicsChandler, Arizona, us 2mo Verification and modeling of mixed-signal power chips (PMICs, battery chargers) using advanced simulation tools and SystemVerilog/Verilog-AMS.
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Senior Verification Tech Lead, Graviton Team
AmazonTel Aviv-Yafo, Tel Aviv, Israel
2mo
Leading verification of complex SoC sub-systems (IO, interconnect, accelerators) for the AWS Graviton server SoC, ensuring logical correctness, performance targets, and seamless hardware-software integration.
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Senior DFT Engineer AnalogdevicesCLOSED-India, Bangalore, Aveda Meta 2mo Define and implement DFT architecture for SoCs to optimize test cost and achieve high coverage, covering scan, MBIST, and post-silicon bring-up.
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Senior Design Verification Engineer HpeSunnyvale, California, United States of America $154k–$311k2mo Develop and execute comprehensive verification strategies for complex digital designs using emulation-based platforms to ensure functional correctness and performance targets prior to silicon tape-out.
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Verification Engineer (all genders) PhilipsHamburg $66k–$66k2mo Conduct integration, system, regulatory, performance, and reliability verification tests for X-ray generators, X-ray tubes, and X-ray segment components to ensure quality, safety, and regulatory compliance.
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