ASIC Verification Engineering
1,077 open positions
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Sr. ASIC Design Verification Engineer (Silicon Engineering) SpaceXAustin - 800 2mo Developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures to enable global connectivity via the Starlink network.
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System Verification Engineer MediaTekHsinChu 2mo Verifying telecom chip requirements for instruments, base stations, and real-world networks to ensure certification by North American operators.
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Staff Engineer ArmBengaluru, India 2mo Lead architecture validation and support integration across multiple architecture components for Arm's CPU and system architectures.
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Hardware Validation & Debug Engineer GraphcoreRemote 2mo Build and validate Graphcore's AI silicon platforms to ensure they function correctly at scale for advanced AI workloads.
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Senior Design Verification Engineer CiscoBelgrade, Serbia 2mo Senior Design Verification Engineer responsible for ASIC functional verification of high-performance networking chips (Cisco Silicon One) using SystemVerilog/UVM, covering architectural discussions, emulation, and simulation support.
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Connectivity Systems Engineer AppleSan Francisco Bay Area, United States of America 2mo Own the pre-silicon emulation environment and infrastructure for wireless SoCs to enable early design verification and bring-up of Bluetooth/UWB silicon.
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Senior Chip Design Verification Engineer NVIDIAIsrael, Tel Aviv 2mo Design and verify core units within Networking silicon chips to ensure high throughput and low latency.
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DFT Design Engineer CadenceAUSTIN 2mo Design for Test (DFT) engineering for SoC/ASIC digital designs, focusing on scan chain insertion, memory testing, and automatic test pattern generation.
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DRAM Verification Engineer MicronHashimoto, Japan 2mo Lead verification efforts for DRAM and emerging memory architectures by developing test cases, simulation environments, and methodologies to ensure functional coverage and design quality.
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Engineer 1 SiFiveHyderabad, India 2mo Verifying complex CPU pipelines and memory subsystems, specifically ensuring architectural and microarchitectural correctness of the Memory Management Unit (MMU).
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Senior Staff Digital Verification Engineer (f/m/d) Renesas-ElectronicsRemote 2mo IC verification expert for sensor applications in automotive and industrial markets, focusing on sensor signal conditioners and analog mixed-signal simulations.
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GPU Design Verification Engineer (GCDV) Samsung Electronics3655 N 1st St, San Jose, CA, USA $180k–$180k2mo End-to-end verification of GPU cores, covering the entire graphics pipeline from input to output, ensuring high-performance graphics rendering meets specifications.
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Senior Staff Physical Verification CAD Engineer MarvellSingapore 2mo Developing next-generation automated design flow and add-on tools for physical verification (PV) to support Marvell's IC design infrastructure and methodology.
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Senior Principal Emulation Engineer NxpBangalore 2mo Lead complex SoC emulation programs and drive end-to-end emulation model development for pre-silicon verification and validation.
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Product Development Engineer AlteraSan Jose, California, United States $106k–$106k2mo Driving thermal characterization, system-level validation, and product performance optimization for next-generation FPGA products from development to high-volume manufacturing.
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Senior Hardware Validation & SI Correlation Engineer SambanovasystemsSan Jose, CA $210k–$210k2mo Validating high-speed electrical interfaces and system-level hardware for next-generation AI server systems to ensure flawless performance between simulation and silicon.
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Functional Subject Matter Expert AccentureBengaluru 2mo Ensure functional correctness of System on Chip (SoC) systems by validating requirements, workflows, and expected system behavior against business processes.
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Senior Principal Design Verification Engineer ON SemiconductorBangalore, Karnataka, India 2mo Define verification strategy and plans for embedded MCU, DSP systems, and cryptography hardware accelerators.
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Analog Mixed-Signal Design Verification Engineer - TeraWave BlueoriginSan Diego, CA, US $230k–$230k2mo Lead mixed-mode design verification methodology for complex System-on-Chips (SOCs) in analog mixed-signal circuits, defining co-simulation EDA environments and developing behavioral models.
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CPU DFT Manager IntelIndia, Bangalore 2mo Lead and technically guide a high-performing DFT team focused on X86 CPU DFT design and validation for silicon and platform solutions.
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