ASIC Verification Engineering
1,076 open positions
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Chip Design Manager NVIDIAIsrael, Tel Aviv 3mo Lead a team of formal verification engineers to verify next-generation NVIDIA networking products and GPU technologies, ensuring design correctness for data centers, HPC, and storage.
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Career Accelerator Program - Mixed Signal Design Verification Engr Texas InstrumentsUnited States 3mo Developing verification plans, SystemVerilog test benches, and simulations for RTL and GLS to ensure first-pass silicon success for mixed-signal systems.
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Staff Engineer SiFiveAhmedabad, India 3mo Drive verification of a next-generation cache-coherent interconnect subsystem for high-performance SoCs, focusing on coherent data movement, protocol correctness, and subsystem integration.
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Senior Firmware Development Engineer MicrosoftUnited States, California, Mountain View 3mo Develop compute-intensive test applications and profiling tools for MAIA hardware systems, focusing on PCIe, memory, network, and TDP workloads to validate functional and performance scenarios.
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Principal Hardware DFT Lead NxpNoida, IN 3mo Architect, implement, and validate advanced DFT strategies for NXP's automotive-grade SoC products, ensuring high fault coverage and test efficiency from pre-tapeout to post-silicon.
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CPU Design Verification Engineer IntelMalaysia, Penang 3mo Pre-silicon functional verification of CPU logic to ensure designs meet microarchitecture specifications.
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AMS Engineer OlixAustin, TX 3mo Senior Mixed-Signal Verification Engineer owning verification of analog and mixed-signal blocks for high-speed IO RX/TX chains in a new AI computing accelerator.
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Design Verification Engineer BroadcomUSA-CA San Jose Innovation Drive $144k–$144k3mo Developing verification environments, agents, and test cases for state-of-the-art SoC and embedded IP subsystems using System Verilog and UVM.
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Lead/Principal DFT Engineer FractileThe Crescent 3mo Designing and implementing Design for Test (DFT) architecture for large AI accelerator System-on-Chips (SoC) to enable high-speed inference and production testing.
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Staff DFT Engineer Renesas-ElectronicsRemote 3mo Designing and implementing DFT architecture and test solutions for complex SoC/ASIC chips to ensure manufacturability and reliability.
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SoC Digital Verification Engineer (m/f/d) AppleMunich, Germany 3mo Develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors for large-scale SoC designs.
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DFT Architect AlteraPenang 15, Penang, Malaysia 3mo Define and govern next-generation DFT architecture for advanced FPGA, SoC, and multi-die silicon platforms, ensuring world-class testability and manufacturability.
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Principal Verification Engineer ON SemiconductorMilan, Lombardia, Italy $66k–$66k3mo Developing comprehensive verification strategies and plans for power management integrated circuits to ensure functional and code coverage.
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Senior Engineer ArmBengaluru, India 3mo Verification engineer developing functional correctness strategies for sophisticated Subsystems and SoCs in Enterprise, Auto, and Client markets.
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Lead DFT Engineer - MBIST GlobalFoundriesIND - Karnataka - Bengaluru - North 3mo Architecting, implementing, and validating advanced Design-for-Test (DFT) solutions for complex System-on-Chips (SoCs), focusing on memory testing and scan insertion.
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Silicon Emulation Engineer WaymoMountain View (US-MTV-EMF690) $175k–$175k3mo Simulate future silicon designs and software on an emulation platform to enable functional and performance validation and left-shift of software development.
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DFT Engineer (Design for Testability) - Staff MicronRichardson, TX 3mo Design, simulation, and validation of next generation High Bandwidth Memory (HBM) architectures and circuit blocks, ensuring robust test coverage across wafer, die, stack, and system in package (SiP) test stages.
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Senior ASIC Design Verification Engineer - Terawave BlueoriginCentral Texas, US $230k–$230k3mo Lead verification planning and execution for complex digital subsystems in next-generation Satellite communication ASICs.
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Lead Design Engineer(Virtual Solution) CadenceSHANGHAI 3mo Design and develop system-level AVIP solutions for emulation/prototyping platforms and build integrated Accelerated Verification IP environments for complex SoC validation.
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Formal Verification - DV EtchedSan Jose 3mo Drive formal verification strategy and execution for custom IP, interface IP, and SoC subsystems in ASICs to prove design correctness and expose deep corner-case bugs.
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