ASIC Verification Engineering
1,076 open positions
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SoC Verification Lead NVIDIAUS, CA, Santa Clara $232k–$232k3mo Lead verification for next-generation AI-enabled SoC designs powering data center AI, client computing, autonomous vehicles, and robotics.
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Engineer, Design MicronAvezzano (AQ), Italy $34k–$57k3mo Design and validate DFT architectures and test strategies for advanced NAND Flash memory products to ensure testability, quality, and manufacturability.
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IC verification engineer MediaTekHsinChu 3mo Developing test patterns for chip bring-up and debugging post-silicon issues to identify design weaknesses.
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Staff Design Verification Engineer SiFiveHsinchu, Taiwan 3mo Ensuring fidelity of new highly configurable RISC-V CPU cores and related IPs for clients in autonomous driving, 5G, wearables, and IoT.
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Associate Staff CAD Engineer - Physical Verification SilabsAustin $125k–$125k3mo Develop and support physical verification rule decks (DRC, LVS, dummy fill, antenna, density, PERC, XOR) and automate verification flows for highly integrated SoCs.
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CPU Design Verification Engineer AlteraBengaluru, Karnataka, India 3mo Develop and execute verification plans to validate Altera's RISC-V processor family logic against architectural and microarchitectural specifications.
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Staff Engineer - ATE Renesas-ElectronicsRemote 3mo Lead post-silicon validation and production testing efforts for silicon devices (SoC/MCU/ASIC) using ATE platforms, managing test development, characterization, and root cause analysis.
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Design Verification Engineering Lead - Silicon One CiscoSan Jose, California, US $211k–$211k3mo Architect and develop DV infrastructure for complex ASICs, ensuring robust verification and coverage for Cisco's data center solutions.
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Principal Engineer, Design Verification Engineering AnalogdevicesUS, TX, Austin, Plaza on the Lake $198k–$198k3mo Architecting and executing pre- and post-silicon verification for digital designs, sub-systems, and SoCs using System Verilog and UVM.
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Digital Design Verification Engineer OlixBristol, UK 3mo Own end-to-end verification of high-throughput digital pipelines supporting multi-GSPS input rates, continuous streaming data paths, and deep pipelining in advanced CMOS nodes.
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Senior Quantum Design Verification Engineer MicrosoftUnited States, Washington, Redmond 3mo Define pre-silicon simulation and post-silicon validation plans for SoC and IP, creating verification environments and tests for RTL/netlist designs while managing repositories and bug tracking.
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Sr. Staff/Staff Design Verification Engineer CerebrasHeadquarters/Sunnyvale Office $250k–$250k3mo Develop and implement verification strategies, detailed tests, and coverage plans for the world's largest AI chip architecture to ensure high-quality design working on first silicon.
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IP Verification Engineer ArmChandler, Arizona $130k–$130k3mo Develop testbenches and test suites for complex subsystems and SoCs to ensure functional verification quality and schedules.
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R&D Digital Design Engineer BroadcomUSA-CA San Jose Innovation Drive $122k–$122k3mo Verification of cutting edge network switch routing designs (L2/L3) for Tomahawk ASICs supporting Scale-Out and Scale-Up AI Networks.
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Physical Design Verification Manager, Annapurna Labs
AmazonCupertino, California, United States
$201k–$201k4mo
Lead end-to-end physical verification strategy for AWS's most complex SoCs (≥100M gates) from floorplan to tape-out.
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Staff Verification Design Engineer SemtechIND - Hyderabad 4mo Perform block and chip-level verification across RTL, gate-level, and analog/mixed-signal domains to ensure tape-out quality and support post-silicon bring-up.
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Digital Design Verification Engineer | Precision ADC Texas InstrumentsTucson, AZ, United States 4mo Develop SystemVerilog/UVM testbenches to verify digital logic, calibration algorithms, and mixed-signal interfaces of high-resolution delta-sigma ADC signal chains.
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DFT Engineer (M, F, D) AppleMunich, Germany 4mo Lead the complete Design for Test (DFT) solution for semiconductor chip projects, ensuring first-tapeout success through architecture, verification, and test vector generation.
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Emulation Engineer
MatXMountain View (HQ) or Remote
$160k–$160k4mo
Building infrastructure, flows, and debug methodology for advanced connectivity SoCs to support high-performance GenAI silicon.
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DFT Engineer GlobalFoundriesRichardson $106k–$106k4mo Designing and deploying advanced Design-for-Test (DFT) solutions for semiconductor chip development, focusing on robust architectures and optimized test methodologies.
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